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Session: Neurophysiology: Biological Neural Networks
Session starts: Thursday 24 January, 10:40
Presentation starts: 11:25
Room: Lamoraalzaal

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Wannaya Ngamkham (Delft University of Technology)
Marijn van Dongen (Delft University of Technology)
Wouter Serdijn (Delft University of Technology)

Abstract:
Cochlear Implants (CI) are prosthetic devices that restore hearing in profoundly deaf patients by bypassing damaged parts of the inner ear and directly stimulating the remaining auditory nerve fibers in the cochlea with electrical pulses. Since the stimulators are implanted inside the body, these devices must be as small as possible. This means avoiding the use of external components, while simultaneously keeping the power consumption as low as possible to avoid the need for big batteries. A current source based stimulator architecture was chosen. First of all the voltage compliance of the current source must be as high as possible to allow for the lowest supply voltage possible. Furthermore the output impedance of the current source needs to be high to guarantee a well defined output current to handle a wide range of electrode-tissue impedances. This is particularly important to achieve charge cancellation in order to prevent electrolysis. This work presents the design of a constant current mode, biphasic neural stimulator circuit for cochlear implants that meets the demands mentioned above. Using a double-loop negative-feedback topology, the output impedance of the current generator is increased, while only a single transistor is needed at the output stage. This means that the compliance voltage of the current source is maximized, which allows the circuit to convey more charge into the tissue. The circuit can provide a biphasic stimulation scheme from a single-ended supply with an amplitude range of 10uA up to 1.05mA for a wide range of electrode-tissue impedances (RL=1k ohm~10k ohm, CL=1nF~10nF). The stimulation current is set by scaling a reference current using a two stage binary-weighted transistor DAC configuration (3 bits HV transistor DAC and a 4 bits LV transistor DAC) to improve the rise and fall times of the stimulation pulses and minimize the area of the circuit. Simulation results, using AMS 0.18m high-voltage CMOS IC, show that the charge error within a cycle (of 600us) is only 0.02%, equivalent to a DC current error of 3nA at the maximum stimulation current with a load of 10k ohm+10nF. The charge mismatch was found to be well below the safety limits. The die area of the chip is 200um × 200um, 5 times smaller than an electrode contact, which is useful for the future to bring the stimulator circuit close to electrode array to increase the number of channels and reduce the area of the device. Measurements of the manufactured chip are currently in progress.